U.S. Pat. No. 5,438,300 describes a frequency multiplier that includes a ring oscillator having a number of logic gates arranged in a plurality of rings. Control inputs enable the selection of individual gates so as to connect them into the ring or, conversely, remove them from the ring. As additional gates are removed, the combined delay imposed by the gates remaining in the ring is reduced and the frequency of the oscillator increases. A variable delay element, such as a group of tri-state inverters connected in parallel, is connected between two of the gates. The oscillator is fine tuned by controlling the delay inserted by the variable delay element. The frequency multiplier also includes a frequency comparator. A reference frequency is passed through a divide-by-K unit and the output of the ring oscillator is passed through a divide-by-N unit, N being greater than K. The frequency multiplier is coarse-tuned by progressively removing additional gates from the ring oscillator, and then fine-tuned by increasing the delay imposed by the variable delay element. At the conclusion of coarse and fine tuning, the frequency multiplier is locked at a frequency which closely approximates a reference frequency multiplied by N/K. When the frequency multiplier ceases to be hooked on a frequency, it enters an idle state in which it consumes no power.